Terafab: One Terawatt of Chips Is Not Yet a Capacity Plan

CC BY 4.0Commercial reuse with attribution

Terafab promises one terawatt of chip output a year. Translating that slogan into wafers, packages, power, and useful compute reveals the missing assumptions that determine whether this is one giant fab, a multi-campus system, or simply an ambition.

A vast retro-future semiconductor complex with autonomous vehicles traveling through its interior as staff work along a fabrication wing

Executive summary

Terafab's headline target is to manufacture 1 terawatt of compute hardware per year. The number signals extraordinary ambition, but it is not yet a semiconductor capacity plan. A watt measures power. It does not reveal how many wafers enter a fab, how many good dies leave it, how those dies are packaged, or how much useful computation the finished systems deliver.

This analysis reads the target as the sum of the rated power of hardware manufactured during a year. That is the most dimensionally coherent interpretation of the public wording, not a measurement rule disclosed by SpaceX. Under this interpretation, two missing assumptions determine the physical scale. If the average device is rated at 1,000 watts, 1 TW implies one billion devices a year. At 100 watts, it implies ten billion. Depending on good devices per wafer, those cases imply anywhere from four million to 250 million annual 300 mm logic wafer equivalents.

Terafab could still become a consequential industrial project. Its proposed combination of logic, memory, photomasks, advanced packaging, system integration, and testing addresses real bottlenecks in AI hardware. For now, however, 1 TW is better read as a systems ambition than as an auditable forecast of factory capacity.

What Terafab has disclosed

The Terafab website describes a vertically integrated complex for logic, memory, and advanced packaging. It pairs a footprint of 100 million square feet with an output target of 1 TW per year, naming AI5 and AI6 for terrestrial applications and a D3 chip for space. The page also says that more than 1 TW of solar capacity would be needed and that one billion Optimus robots would "do the work." That last phrase appears to describe automation at industrial scale, not one billion committed customers or units of terminal demand.

The SpaceX final prospectus describes Terafab as a long-term goal. It links terrestrial chips to products such as Optimus and vehicles, and space chips to orbital compute. It also says that timelines, milestones, and capital requirements have not been determined, that Tesla and Intel are not obligated to participate, and that SpaceX expects to keep sourcing a significant portion of its semiconductors from third parties.

A Texas JETI application supplement supplies more physical detail. It describes as many as four phases, sub-2-nanometer-class manufacturing through technology partners, and a possible capital range of $55 billion to $119 billion for initial phases and expansion. Its scope runs from chip design and photomasks through wafer fabrication, packaging, integration, and testing.

Together, the disclosures establish something broader than a conventional leading-edge logic fab. They do not provide the translation from 1 TW into the metrics needed to operate one: product mix, wafer starts, yield, package throughput, or a ramp schedule.

Three different uses of a terawatt

Terafab's website places three terawatt figures close together: 1 TW of annual compute-hardware output, more than 1 TW of solar capacity, and roughly 0.5 TW of average U.S. electricity use. The common unit hides three different accounting boundaries.

The U.S. Energy Information Administration explains the basic distinction: watts measure power, while watt-hours measure energy used over time. The United States consumed 4.20 trillion kilowatt-hours of electricity in 2025. Spread across 8,760 hours, that is an average end-use load of about 479.5 GW, or 0.48 TW, consistent with Terafab's comparison.

This does not mean that a factory producing 1 TW of rated hardware consumes 1 TW continuously, or that 1 TW of solar nameplate capacity supplies 1 TW at every moment. Solar capacity needs a capacity factor to become annual generation. Hardware output needs a defined power convention and production period. Deployed compute needs actual power draw and utilization. Those figures can coexist, but they cannot be compared as though they measure the same thing.

The missing denominator changes the factory

Suppose 1 TW means the combined rated power of compute devices manufactured in one year. The first conversion is:

Devices per year = 1,000,000,000,000 watts / rated watts per device

The second connects devices to logic wafers:

Annual 300 mm logic wafer equivalents = devices per year / good logic devices per wafer

Neither denominator is public. The matrix therefore tests sensitivity rather than forecasting Terafab's product mix.

A nine-cell sensitivity matrix showing annual 300 millimeter logic wafer equivalents from four million to 250 million under different assumptions for rated device power and good devices per wafer.
Illustrative lower-bound logic wafer equivalents. The calculation excludes memory wafers, chiplets, packaging losses, test fallout, spares, and other silicon in a finished system.

The 1,000-watt row has a present-day reference point. NVIDIA's HGX B200 product carbon footprint summary says a B200 GPU can be configured up to 1,000 watts. This is an anchor for the power class, not a claim that Terafab will manufacture B200-like devices.

At 1,000 watts per device, the target implies one billion devices annually. Forty good devices per wafer would require 25 million logic wafer equivalents; 250 good devices per wafer would require four million. Both satisfy the same headline target, yet one factory is more than six times larger. At 100 watts per device, even the most favorable wafer assumption shown implies 40 million wafer equivalents a year.

For order-of-magnitude context, TSMC reported more than 17 million 12-inch-equivalent wafers of annual capacity in 2025. That total spans TSMC's nodes, product types, and manufacturing sites. It is not like-for-like with a hypothetical Terafab logic stream and should not be used as a direct capacity multiple. It does show that several plausible-looking paths to 1 TW would be vast by current industry standards.

The matrix is deliberately favorable. A modern AI package may contain multiple logic dies, high-bandwidth memory stacks, interposers, and other components. Adding those requirements, plus package yield, test loss, and spare capacity, would increase the manufacturing footprint.

Watts are not a measure of useful compute

Even complete manufacturing denominators would not make watts a sufficient output metric. A watt does not say how much work a chip performs. Architecture, precision, memory bandwidth, software, sparsity, workload, and utilization all matter. A vehicle inference chip, a training accelerator, and a radiation-tolerant orbital processor can have the same power rating while delivering different kinds and amounts of work.

The metric also rewards the wrong direction. If a design team doubles performance per watt while holding useful compute constant, the reported terawatts of hardware fall by half. The product improves, but the headline metric moves backward. A less efficient device can increase "terawatt output" without increasing useful work.

Rated power remains essential for power delivery, cooling, rack design, and generation planning. It becomes misleading when used alone as a measure of manufacturing output. A better disclosure would pair units and rated power with workload-specific performance for each product category, keeping training, inference, vehicles, robotics, and orbital compute separate.

Demand is the second scale test

Terafab's proposed scale depends on products that have not reached the volumes implied by the project. The prospectus identifies internal demand channels, but it does not turn future Optimus, vehicle, launch, or orbital-compute ambitions into purchase commitments.

This creates a circular dependency. A captive fab needs steady demand to absorb fixed costs and sustain manufacturing learning. Tesla and SpaceX products might become easier to scale if Terafab succeeds, while Terafab becomes economical only if those products reach very large volumes.

TSMC offers a useful contrast. Its 2025 annual report says it manufactured 12,682 products for 534 customers using 305 technologies. Customer and product diversity can smooth utilization across cycles. Terafab could gain tighter coordination between design and manufacturing, but it would concentrate utilization risk in a narrower group of internal road maps.

The proposed four-phase structure is therefore more than a construction detail. Each phase can serve as an option: build a bounded module, measure yields and internal demand, then expand when the next phase has a defensible economic case. The Texas filing's $55 billion to $119 billion development envelope and the prospectus's statement that capital requirements remain undetermined can both be true if one describes a possible site plan and the other the company's present commitment.

What would make the target auditable

Suppliers, utilities, policymakers, and investors do not need every process secret. They do need a bridge from ambition to throughput.

That bridge starts with annual units by product class and a precise power convention: per die, package, board, server, or complete system, using typical or maximum draw. It then needs monthly wafer starts for logic, memory, interposers, and photomasks, accompanied by good-die and package-yield ranges. Packaging and test capacity must be stated separately, particularly where high-bandwidth memory integration can become the constraint.

A phased schedule should identify pilot production, qualification, risk production, and volume milestones. Once products deploy, workload-specific performance, utilization, and average power should sit beside rated watts. These measures would reveal whether vertical integration reduces cycle time and cost or simply moves the bottleneck from logic to memory, packaging, or test.

The most informative near-term milestone is not 1 TW. It is a smaller, fully specified production module with named products, known process technology, qualified package flows, measurable yield, and committed internal demand.

A systems ambition awaiting factory metrics

The 1 TW goal has one analytical virtue: it directs attention beyond transistor fabrication. AI infrastructure is a system of logic, memory, packaging, power, cooling, software, and deployment. Terafab's proposed scope recognizes that a leading-edge wafer fab alone does not solve the supply problem.

The current disclosures still lack the boundaries needed to convert 1 TW into wafers, packages, capital intensity, electricity demand, or useful compute. The sensitivity range is not a criticism of one chosen assumption. It shows that no assumption has been disclosed, and that reasonable inputs produce radically different factories.

For now, 1 TW describes the scale of hardware SpaceX wants Terafab to support. It does not yet describe capacity that suppliers can plan around, utilities can provision, or investors can model. The claim becomes a capacity plan when the company publishes its denominators, product mix, bottlenecks, and ramp.

Sources

This analysis uses public information available through August 15, 2026. Company statements are treated as claims unless corroborated by a filing or government source. The wafer matrix is a lower-bound sensitivity analysis, not a prediction of Terafab's product mix, yields, or final bill of materials.